IP Release & Verification Engineer

AMD - Advanced Micro Devices

Iasi, Romania

THE ROLE

We are looking for an adaptive, self-motivated Silicon Design Engineer to work on IP Release & Verification Engineering processes. As a key contributor in Infinity (Data) Fabric IP, you will be the critical link between the core IP development team and the various System-on-Chip (SoC) product integration teams. You will assist in preparing IP releases, validating deliverables and ensure that the IP milestone drops are high-quality, fully documented, and meet critical SoC project schedule. You will also be providing first-level support for integration issues, debug and analysis for failures.

THE PERSON

You are a detail-oriented engineer with a passion for modern, complex processor architecture, digital design, and/or verification in general. You have strong analytical and problem-solving skills and comfortable using industry-standard tools to ensure smooth IP integration. You are a team player who has excellent communication skills and enjoys collaborating with other engineers from different sites/time zones in a fast-paced environment.

KEY RESPONSIBILITIES

Collaborate with architects, IP designers, verification, physical design, and program management teams to understand new features, ensure smooth integration and timely deliver;
Build test plan documentation, accounting for interactions with other hardware/software features/components;
Write and implement both directed and random verification tests;
IP Release support: milestone drop delivery to SoC team. Ensure deliverables are complete, accurate, and meet project timelines;
Integration issue triage: provide first level of support for integration-related issues, helping to identify whether problems originate from IP, flow, or environment;
Debug & Analysis: Use simulation and debug tools (e.g., VCS, Verdi) to analyze failures and support root cause identification;
Work with RTL and firmware engineers to resolve design defects;
Maintain and update IP documentation, including release details, integration guidelines, feature lists and known issues;
Ensure changelist integration;
Support automation efforts using scripting languages (Python, Perl) to improve release and validation flows.

PREFERED SKILLS AND EXPERIENCE

Good understanding of computer architecture, interconnects and cache coherency;
Knowledge/experience on digital design and verification processes, methodologies like UVM;
Ability to analyze simulation results and assist in resolving technical issues. Familiarity with simulation tools (e.g., VCS), emulation, and debug tools;
Object Orientated Programming knowledge (we use C++ and System Verilog);
Scripting skills (Perl, Shell, Ruby, Python);
Experience working in a Unix/Linux environment;
Advanced verbal and written English.

NICE TO HAVE

Direct experience with Verilog simulators (ModelSim, VCS, Eda Playground, etc.);
Exposure to scripting and automation tools to streamline and enhance modeling workflows;
Familiarity with formal verification concepts and tools is a plus.

PERSONAL COMPETENCIES

Analytical thinking & goal-oriented, eager to learn;
Self-driven, but capable of working within a team;
Strong desire for personal achievement;
Excellent communication and teamwork skills, with the ability to work with cross-functional teams in a global environment.