Design for Test Engineer (DFT)

Design for Test Engineer (DFT)

Qualcomm

Cork, Ireland

About The Role

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Responsibilities will include:

• Implementation of advanced DFT/DFD (design for test/design for debug) techniques for low power, high performance and highly integrated SoCs;
• Deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield learning;
• Deployment and implementation of advanced DFT/DFD (design for test/design for debug) techniques for low power, high performance and highly integrated SoCs;
• Deployment of DFT methodologies that reduce test cost, increase production quality and enhance yield learning.

What are we looking for?

• Bachelor's degree in Science, Engineering, or related field;
• ASIC design, verification, or related work experience;
• Strong fundamental knowledge of DFT/DFD techniques;
• Understanding of core-based test methodology and scan isolation;
• Knowledge in fault modelling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced DFT models;
• Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing;
• Experience with industry ATPG tools Synopsys Tetramax, Cadence Encounter Test or Siemens Tessent tools;
• Experience with Synopsys DFTCompiler or Fusion Compiler scan insertion;
• Direct experience in silicon bring-up, debug, and validation of DFT features on ATE;
• Experience with formal verification tools such LEC, Formality, etc.;
• Knowledge in LowPower designs, UPF and experience in low power check tools like Conformal Low Power;
• Experience in Logic Design, VHDL, Verilog RTL, verification, Synthesis and static timing analysis;
• Experience with industry simulation tools such as VCS, Modelsim, or others;
• Working knowledge in TCL, Python or Perl.

Minimum Qualifications

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience; OR
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience; OR
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.