Senior Safety Verification Engineer

Senior Safety Verification Engineer

Arm

Cambridge, United Kingdom

Role Overview

We are looking for a Safety Verification Engineer to join our engineering team and contribute to the verification of safety-critical hardware designs and safety mechanisms.

In this role, you will develop and execute verification strategies focused on functional safety, including verification of safety mechanisms, leading to safety certification of the released product. You will work closely with design, architecture, and functional-safety teams to demonstrate that designs meet their defined safety requirements and comply with applicable standards, including ISO 26262 and IEC 61508.

Key Responsibilities

• Collaborate closely with RTL designers and architects to understand specifications and microarchitecture details.
• Develop and execute verification plans for functional-safety requirements and safety mechanisms at IP, subsystem, and/or SoC level.
• Develop and maintain verification environments, testbenches, assertions, checkers, and coverage models using SystemVerilog/UVM and related verification technologies.
• Debug simulation failures, identify root causes, and collaborate with design engineers to resolve issues.
• Trace safety requirements to verification activities and provide objective evidence of verification completeness.
• Contribute to verification documentation and safety work products required by ISO 26262, IEC 61508, and internal functional-safety development processes.
• Support reviews of safety requirements, safety mechanisms, FMEDA assumptions, fault models, and verification results.
• Contribute to automation and continuous improvement of regression, coverage-analysis, and reporting flows.

Required Skills and Experience

• 5+ years of experience in IP, subsystem, or SoC verification, with a Bachelor's or Master's degree in Electronics, Electrical, or Computer Engineering.
• Strong proficiency in SystemVerilog, Verilog, and C/C++.
• Experience with UVM or other industry-standard verification methodologies.
• Experience developing constrained-random verification environments and reusable verification components.
• Experience in SoC verification and test development using C/C++.
• Familiarity with functional-safety concepts and standards, particularly ISO 26262 and/or IEC 61508.
• Experience with scripting languages such as Python, Perl, or similar.
• Strong debugging, analytical, and problem-solving skills.
• Strong interpersonal and communication skills, with the ability to collaborate effectively across geographically distributed teams.

Nice-to-Have Skills and Experience

• Experience with Arm-based designs and/or Arm system architectures.
• Experience with AMBA protocols such as AXI, AHB, and APB.
• Experience with clock domain crossing (CDC), reset domain crossing (RDC), and power-aware verification.
• Exposure to low-power design techniques and UPF/CPF methodologies.
• Knowledge of FMEDA, safety analysis, and semiconductor hardware safety metrics.
• Familiarity with safety architectures and mechanisms such as lockstep CPUs, ECC, parity, watchdogs, clock/reset monitors, memory protection, etc.
• Familiarity with assertions and ABV, formal verification, and/or gate-level simulation.

What Success Looks Like

A successful Safety Verification Engineer combines strong semiconductor verification fundamentals with a functional-safety mindset.

You will be able to translate safety requirements and fault hypotheses into effective verification scenarios, execute and analyze fault-injection campaigns, identify gaps in safety mechanisms, and produce clear verification evidence that supports compliance with ISO 26262, IEC 61508, and product-level safety objectives.