SoC Memory Performance Engineer - Platform Architecture

Apple

Munich, Germany

In this role, you will be a member of the Platform Architecture team, working with hardware and software engineering groups to shape the architecture of Apple's future System-on-Chip (SoC). We are seeking an energetic and highly motivated SoC performance engineer to drive development of our memory system and caches for the next-generation of wearable products like Vision Pro & Cellular/5G applications.

The position calls for independent performance modeling and simulation, documentation, and collaboration with design/software teams. We are looking for SoC architects with a passion to innovative new hardware concepts and model them in C++/Python to demonstrate their value and impact.

Key Qualifications

Solid knowledge of cache management and memory controller for DRAM technologies. Prior experience on writing a memory simulator using C++ is a big plus.
Extensive experience with micro-architectural performance modeling, architectural exploration, performance validation and correlation
Proficient programming skills in SystemC, C++ or equivalent languages and related software engineering principles
Experience with scripting languages like Python, Perl, Lua, Bash
Significant experience in architectural research or in development of embedded systems projects
Experience with on-chip interconnect fabrics, caches, and memory/DRAM controllers, quality-of-service architecture.
Ability to study a problem in depth, design experiments, analyze data and present results in wider forums
Strong communication and documentation skills.
Ability to fluently speak and write in English

Description

You will conduct architectural and micro-architectural feature exploration and validation using the performance model for Apple silicon.

You will have responsibilities for developing the SoC hardware solutions that drive the architecture of Apple’s future System-on-Chips. Your work will be highly visible and critical to delivering the best performance and power efficiency in Apple’s future products. You will be expected to collaborate with all the hardware and software teams that are part of Apple’s SoC development.

Your responsibilities will include, but are not limited to:

Create C++ based performance models of proposed architectural solutions and features.
Execute simulation based performance analysis for our products to compare and propose architectural design alternatives.
Defining test plans and test planning methodology to secure the performance targets towards the product.
Gathering, analyzing, and validating measured and simulated results to compare architectural design alternatives.
Improve Apple’s modeling platform by developing APIs, tools, and optimal standard examples that can be used throughout the company.
Tuning and validating future SoC HW/SW for the best user experience.
Interface and collaboration with cross-functional teams: architecture, hardware and software teams for collaborative debug, and correlation studies.
Some international travel is required for this position.